Selection reference · illustrative scenario
Start with the host clock requirement
A gateway may need PHY references, an MCU clock and RTC timing. Distinguish crystal ports from external clock inputs. Follow each host reference design for frequency, signaling, loading and sequencing instead of prescribing one frequency to every device.
Engineering review
For crystals, check CL, ESR, drive and cold start. For oscillators, check signaling, voltage, error budget and start-up. Include actual board temperature, supply ripple and link testing.
Buyer review
Provide the existing brand and code, sample quantity, production plan and delivery target. For SCTF or CREC alternatives, prepare a difference review before customer application validation.
Scenario: intermittent cold start after a change
If room-temperature operation is normal but cold starts fail intermittently, compare ESR, CL, host settings and probe loading. Use multiple boards and repeated power cycles. Let evidence guide sample selection without assuming the oscillator is necessarily the cause.
Inquiry & validation checklist
- PHY/MCU and reference design
- CL/ESR or signaling
- Cold and supply-corner starts
- Samples, volume and delivery
