Selection reference · illustrative scenario
Draw the clock relationships
List reference clocks for the FPGA, video processor and other receivers. Distinguish independent domains from clocks requiring a defined relationship. Multiple independent oscillators do not automatically replace a synchronized multi-output source.
Engineering: electrical and timing review
Review signaling, coupling, termination, jitter band and enable behavior against receiver requirements. System architecture determines the need for tuning, PLL tracking or synchronization.
Procurement: order codes, not family names
A family can offer different frequencies, outputs and enable functions. Record each BOM clock purpose and full suffix, and retain configuration approval for programmable options.
Scenario: interface-compatible, different enable timing
A candidate with the same frequency and signaling still needs enable-to-valid-clock and reset-release review. Validate system boot and sleep recovery before approval.
Inquiry & validation checklist
- FPGA / receiver model
- Clock tree and synchronization
- Signaling, jitter and enable behavior
- Configuration and full suffix
